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Tri path Technol og y, I nc. - Techni cal I nformation
TAA2008 STEREO 9W (8) CLASS-TTM DIGITAL AUDIO AMPLIFIER USING DIGITAL POWER PROCESSINGTM TECHNOLOGY
TECHNICAL INFORMATION Revision 1.0 - May 2006
GENERAL DESCRIPTION
The TAA2008 is a 9W/ch continuous average two-channel Class-T Digital Audio Power Amplifier IC using Tripath's proprietary Digital Power ProcessingTM technology. The TAA2008, in a QFN package, along with extremely high efficiency, allows for a very compact amplifier design. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
APPLICATIONS FEATURES
LCD TV's LCD Monitors Plasma TV's Computer/PC Multimedia Battery Powered Systems
BENEFITS
Fully integrated solution with FETs Compact packaging and board design Reduced system cost with no heat sink Dramatically improves efficiency versus ClassAB Signal fidelity equal to high quality linear amplifiers High dynamic range compatible with digital media such as CD, DVD, and Internet audio Capable of driving a wide range of load impedances
TYPICAL PERFORMANCE
THD+N versus Output Power
10 VDD = 12V f = 1kHz 5 A = 12V/V V BW = 22Hz - 20kHz(AES17) 2 R L =16 1 R L =8 R L =6 R L =4
Class-T architecture Single Supply Operation "Audiophile" Quality Sound 0.025% THD+N @ 5W, 8 0.1% IHF-IM @ 1W, 8 6.3W @ 8, 0.1% THD+N 3.5W @ 16, 0.1% THD+N High Power 14.25W @ 6, 10% THD+N 9W @ 8, 10% THD+N 5W @ 16, 10% THD+N Extremely High Efficiency 89% @ 5W, 16 86% @ 9W, 8 Dynamic Range = 98.5 dB Mute and Sleep modes Improved turn-on & turn-off pop suppression Over-current protection with automatic restart circuit Over-temperature protection Space saving 32-pin 8mm x 8mm x 1mm QFN package with exposed pad
REF OVRLDB AGND2 V5A OAOUT1 INV1 MUTE N C 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 AGND1 V5D DCAP1 DCAP2 5VGEN CPUMP PGND1 VDDA
0.5
0.2 0.1 0.05
OAOUT2 INV2 BIASCAP AGND3 SLEEP FAULT PGND2 DGND
THD+N (%)
16 15 14 13 12 11 10 9
0.02
N C OUTP1 VDD1 OUTM1 OUTM2 VDD2 OUTP2 N C
0.01
1
2
3
4
5
6
7
8
9 10
20
Output Power (W)
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A B S O L U T E M A X I M U M R A T I N G S (Note 1)
SYMBOL VDD V5 SLEEP MUTE TSTORE TA TJ ESDHB ESDMM Supply Voltage Input Section Supply Voltage SLEEP Input Voltage MUTE Input Voltage Storage Temperature Range Operating Free-air Temperature Range Junction Temperature ESD Susceptibility - Human Body Model (Note 2) ESD Susceptibility - Machine Model (Note 3) PARAMETER Value 16 6.0 -0.3 to 6.0 -0.3 to V5+0.3 -40 to 150 0 to 70 150 2000 200 UNITS V V V V C C C V V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Human body model, 100pF discharged through a 1.5K resistor. Note 3: Machine model, 220pF - 240pF discharged through all pins.
O P E R A T I N G C O N D I T I O N S (Note 4)
SYMBOL VDD VIH VIL Supply Voltage (Note 5) High-level Input Voltage (MUTE, SLEEP) Low-level Input Voltage (MUTE, SLEEP) PARAMETER MIN. 8.5 3.5 1 TYP. 12 MAX. 14.0 UNITS V V V
Note 4: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits. Note 5: Operation above 13.2V requires the use of low and high side schottky diodes as well as 220uF for CSW. See the Application Section for additional information
THERMAL CHARACTERISTICS
SYMBOL JA PARAMETER Junction-to-ambient Thermal Resistance (note 6) VALUE 22 UNITS C/W
Note 6: The JA value is based on the exposed pad being soldered down to the printed circuit board. The exposed pad must be soldered to an exposed copper area on the printed circuit board for proper thermal and electrical performance.
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E L E C T R I C A L C H A R A C T E R I S T I C S (Note 7)
See Test/Application Circuit. Unless otherwise specified, VDD = 12V, f = 1kHz, Measurement Bandwidth = 20kHz, RL = 8, TA = 25 C, package exposed pad soldered to the printed circuit board.
SYMBOL PO PARAMETER Output Power (Continuous Average/Channel) CONDITIONS THD+N = 0.1% RL = 6 RL = 8 RL = 16 RL = 6 RL = 8 RL = 16 TBD MIN. TYP. 8 6.3 3.5 12 9 5 14.25 12 6.3 31 0.25 61 0.022 0.1 98.5 50 65 85 60 75 65 89 50 3.5 1 A-Weighted, input AC grounded 100 150 150 0.5 36 2 75 MAX. UNITS W W W W W W W W W mA mA mA % % dB dB dB dB dB % mV V V V
THD+N = 10%
VDD = 13.2V, THD+N=10% RL = 6 RL = 8 RL = 16 IDD,MUTE IDD, SLEEP Iq THD + N IHF-IM SNR CS PSRR VOFFSET VOH VOL eOUT Mute Supply Current Sleep Supply Current Quiescent Current Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Power Supply Rejection Ratio Power Efficiency Output Offset Voltage High-level output voltage (FAULT & OVERLOAD) Low-level output voltage (FAULT & OVERLOAD) Output Noise Voltage MUTE = VIH SLEEP = VIH VIN = 0 V PO = 5W/Channel 19kHz, 20kHz, 1:1 (IHF) A-Weighted, POUT = 9W, RL = 8 f = 1 kHz 20 Hz < f < 20 kHz VDD = 9V to 13.2V Vripple = 100mVrms, f=1kHz POUT = 5W/Channel, RL = 16 No Load, MUTE = Logic Low
Note 7: Minimum and maximum limits are guaranteed but may not be 100% tested.
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PIN DESCRIPTION
Pin 1, 29 2, 30 3 4, 24, 27 5 6 7, 18 8 10, 12; 15, 13 11, 14 17 19 20 21,22 Function OAOUT2, OAOUT1 INV2, INV1 BIASCAP AGND3, AGND1, AGND2 SLEEP FAULT PGND2, PGND1 DGND OUTP2 & OUTM2; OUTP1 & OUTM1 VDD2, VDD1 VDDA CPUMP 5VGEN DCAP2, DCAP1 Description Input stage output pins. Single-ended inputs. Inputs are a "virtual" ground of an inverting opamp with approximately 2.4VDC bias. Input stage bias voltage (approximately 2.4VDC). Analog Ground When set to logic high, device goes into low power mode. If not used, this pin should be grounded A logic high output indicates thermal overload, or an output is shorted to ground, or another output. Power Grounds (high current) Digital Ground. Connect to AGND locally (near the TAA2008). Bridged output pairs Supply pins for high current H-bridges, nominally 12VDC. Analog 12VDC. Connect to same supply as VDD1 and VDD2. Charge pump output (nominally 10V above VDDA) Regulated 5VDC source used to supply power to the input section (pins 23 and 28). Charge pump switching pins. DCAP1 (pin 22) is a free running 300kHz square wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 21) is level shifted 10 volts above DCAP1 (pin 22) with the same amplitude (12Vpp nominal), frequency, and phase as DCAP1. Digital 5VDC, Analog 5VDC Internal reference voltage; approximately 1.0 VDC. A logic low output indicates the input signal has overloaded the amplifier. When set to logic high, both amplifiers are muted and in idle mode. When low (grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. This pin should be tied to GND if not used. Not connected. Not bonded internally.
23, 28 25 26 31 9, 16, 32
V5D, V5A REF OVERLOADB MUTE NC
TAA2008 PINOUT
32-pin QFN (Top View)
OVRLDB OAOUT1 INV1 MUTE 30 29 AGND2 REF V5A NC 1 2 3 4 5 6 7 8 12 11 10 13 14 15 9
31 32
28
27
26
25
OAOUT2 INV2 BIASCAP AGND3 SLEEP FAULT PGND2 DGND
24 23 22 21 20 19 18 17
AGND1 V5D DCAP1 DCAP2 5VGEN CPUMP PGND1 VDDA
16
OUTM1 OUTM2 VDD2 OUTP2 NC
VDD1
OUTP1
NC
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APPLICATION / TEST CIRCUIT
T AA2008
OA OUT1 29 RF 20K INV 1 RI 20K CA 0.1uF (Pin 4)
5V
V DD1 V DD1 Lo 10uH, 2A
CI 2.2uF +
30
15 OUTP1
D O **
BIA SCA P
3
Proces s ing & Modulation
PGND1 V DD1
(Pin 18) (Pin 18) V DD1 Lo 10uH, 2A
Co 0.22uF
CZ 0.22uF C DO 0.01uF RL 8 or 16
13 OUTM1
Co 0.22uF
RZ 10 , 1/4W
D O ** PGND1 (Pin 18) FA ULT (c onnec t to MUTE f or auto res tart) OV ERLOA DB V DD2
5V MUTE
31
6 26
CI 2.2uF + OA OUT2 RF 20K INV 2 RI 20K
1
V DD2 Lo 10uH, 2A
2
10 OUTP2
D O **
25
(Pin 24) R RE F 8.25K , 1%
REF
Proces s ing & Modulation
PGND2 V DD2
(Pin 7) (Pin 7) V DD2 Lo 10uH, 2A
Co 0.22uF
CZ 0.22uF C DO 0.01uF
22
+12V 1M CD 0.1uF
DCA P1
12 OUTM2
Co RZ 0.22uF 10 , 1/4W
RL 8 or 16
D O **
21 5
DCA P2 PGND2 SLEEP CPUMP 19
(Pin 7)
N.C.
0.1uF
23
CS 0.1uF To Pin 20 CS 0.1uF
+
V 5D A GND1 V5A A GND2 A GND3
5V V DDA DGND 5V GEN
17 8 20
CP 1uF CS 0.1uF CS 0.1uF To Pins 23,28
24 28 27 4
V DD1 PGND1
14 18
C SW 0.1uF
+
V DD (+12V ) CS W **
100uF, 16V
9
16 NC 32
NC
NC V DD2 PGND2
11 7
C SW 0.1uF
Note: A nalog and Digital/Pow er Grounds mus t be c onnec ted loc ally at the TA A 2008 A nalog Ground Digital/Pow er Ground ** For V DD v oltages abov e 13.2V , output diodes (DO ) s hould be us ed and the v alue of CS W s hould be inc reas ed to 220uF. A ll Diodes are Motorola MBRS130T3 or equiv alent.
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E X T E R N A L C O M P O N E N T S D E S C R I P T I O N (Refer to the Application/Test Circuit)
Components RI RF CI RREF CA CD CP
Description Inverting Input Resistance to provide AC gain in conjunction with RF. This input is biased at the BIASCAP voltage (approximately 2.4VDC). Feedback resistor to set AC gain in conjunction with RI; A V = 12(RF / RI ) . Please refer to the Amplifier Gain paragraph in the Application Information section. AC input coupling capacitor which, in conjunction with RI, forms a highpass filter at
fC = 1 (2RICI )
CS CSW
CZ RZ
DO
LO
Bias resistor. Locate close to pin 25 (REF) and ground at pin 24 (AGND1). BIASCAP decoupling capacitor. Locate close to pin 3 (BASCAP) and ground at pin 4 (AGND3). Charge pump input capacitor. This capacitor should be connected directly between pins 21 (DCAP2) and 22 (DCAP1) and located physically close to the TAA2008. Charge pump output capacitor that enables efficient high side gate drive for the internal H-bridges. To maximize performance, this capacitor should be connected directly between pin 19 (CPUMP) and pin 17 (VDDA). Please observe the polarity shown in the Application/ Test Circuit. Supply decoupling for the low current power supply pins. For optimum performance, these components should be located close to the pin and returned to their respective ground as shown in the Application/Test Circuit. Supply decoupling for the high current, high frequency H-Bridge supply pins. These components must be located as close to the device as possible to minimize supply overshoot and maximize device reliability. Both the high frequency bypassing (0.1uF) and bulk capacitor (100uF/220uF) should have good high frequency performance including low ESR and low ESL. Recommended capacitor families include Nichicon HE series and Panasonic FM series for thru-hole types. Qualified SMT electrolytics include Nichicon UD series and Panasonic FK series. Zobel Capacitor. Zobel resistor, which in conjunction with CZ, terminates the output filter at high frequencies. The combination of RZ and CZ minimizes peaking of the output filter under both no load conditions or with real world loads, including loudspeakers which usually exhibit a rising impedance with frequency. Schottky diodes that minimize undershoots and overshoots of the outputs with respect to power ground and VDD during switching transitions. These components are recommended for supply voltages above 13.2V. For maximum effectiveness, these diodes must be located close to the output pins and returned to their respective PGND. Please see Application/Test Circuit for ground return pin. Output inductor, which in conjunction with CO and CDO, demodulates (filters) the switching waveform into an audio signal. Forms a second order filter with a cutoff frequency of f C = 1 ( 2 L O C TOT ) and a quality factor of
Q = R L C TOT
CO CDO
2 L O C TOT where CTOT = CO || 2 * CDO.
Output capacitor. Differential Output Capacitor. Differential noise decoupling for reduction of conducted emissions. Must be located near chassis exit point for maximum effectiveness.
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TYPICAL PERFORMANCE
1
TH D +N versus Frequency
10
TH D +N versus Output Power
R L = 6 f = 1kHz 5 A = 12V/V V BW = 22Hz - 20kHz(AES17)
2
V D D = 12V P O = 1W 0.5 BW = 22Hz - 22khz
0.2
0.1
VDD =12V
1
0.05 % 0.02
TH D +N (%)
R L = 8
0.5
VDD =13.2V
R L = 16
0.01
0.2
0.1
0.005
0.05
0.002
0.02
0.001 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
0.01
1
2
3
4
5
6
7
8
9
10
20
Output Power (W )
Efficiency and Power D issipation versus Total output Power
100 90 80 70 E fficienc y 4 5
E fficiency and Power D issipation versus Total output P ower
100 90 80 70 Power Diss ipation Efficiency
2
Pdiss (W )
Eff (%)
50 40 30 20 10 0 0 4 8 12 16 20 Total Output P ower (W )
VD D = 12V RL = 8 f= 1 kH z BW = 2 2H z - 2 0kH z(AES17)
E ff (%)
60
3
60 50 40 30
1
P ower Dissipation
2
1
20 10
VD D = 12V R L = 16 f= 1kH z BW = 2 2H z - 20 kH z(AES17)
0
0 0 2 4 6 Total Output Power (W ) 8 10
0 12
Efficiency and Power D issipation versus Total output Power
100 90 P ower Dissipation 80 E fficiency 70 70 4 80 5 100 90
Efficiency and Power D issipation versus Total output Power
10
E fficiency
8
Pdiss (W )
Eff (%)
50 40 30 20 10 0 0 5 10 15 20 25 Total Output P ower (W )
VD D = 12 V RL = 6 f= 1kH z BW = 22H z - 20kH z(AES17 )
Eff (%)
60
3
60 50 40 30 P ower Dissipation
6
2
4
1
20 10
VD D = 13 .2 V RL = 6 f= 1kH z BW = 22H z - 20kH z(AES17 )
2
0
0
0 30
0
5
10
15
20
25
Total Output P ower (W )
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Pdiss (W)
P diss (W )
Tri path Technol og y, I nc. - Techni cal I nformation
TYPICAL PERFORMANCE
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
-90 d B V
Intermodulation D istortion
19kHz, 20kHz 1:1 P O = 1W VD D = 12V R L = 8 32k FFT F S = 65kHz B W = <10Hz - 80kHz
+0
N oise Floor
V D D = 12V -10 R L = 8 32k FFT F S = 65kHz -20 B W = 22Hz - 20kHz(A E S 17)
-30 -40 -50 -60 -70 -80
FFT (dBr)
-110
-100
-120 -130 20 50
-110
100
200
500
1k Frequency (Hz )
2k
5k
10k
20k
30k
-120 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Output P ower versus S upply V oltage
14 12 10 8 6 4 2 0 9
R L = 8 f = 1kH z BW= 22H z - 20kH z(AES17) TH D +N = 10%
Output Power versus Supply Voltage
8 7 6
R L = 16 f = 1kH z BW= 22H z - 20 kH z(AES17)
Output P ower (W )
Output Power (W )
TH D +N = 10%
5 4 3 2 1 0
TH D +N = 1%
TH D +N = 1%
10
11
12
13
14
9
10
11
12
13
14
S upply V oltage (V)
Supply Voltage (V)
Output P ower versus S upply V oltage
16 14 12
R L = 6 f = 1kH z BW= 2 2H z - 2 0kH z(AES17) TH D +N = 10%
Maximum S upply C urrent versus S upply V oltage
2.75 2.50
TH D =N = 10% f= 1kH z BW= 22H z - 20kH z(AES17) Both chanels driven
Max. S upply C urrent (IDC )
RL = 6
2.25 2.00 1.75 1.50 1.25 1.00 0.75
R L = 16 RL = 8
Output P ower (W )
10 8 6 4 2 0
TH D +N = 1%
9
9
10
11
12
13
14
10
11
12
13
14
S upply V oltage (V)
Supply V oltage (V )
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TYPICAL PERFORMANCE
Channel Separation
+0
T T T T T T T T
Frequency Response +3 +2.5 +2 +1.5 VD D = 12V P O = 1W
-10 -20 -30
VD D = 12V R L = 8 P O = 1W BW = 22Hz - 22kHz
R L = 16 RL = 8 R L = 6
+1
-40 d B r -50 -60 -70 -80 -90 -100 -110 20
d B r
+0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3
20
50
100
200
500 Hz
1k
2k
5k
10k
20k
50
100
200
500 Hz
1k
2k
5k
10k
20k
APPLICATION INFORMATION Layout Recommendations
The TAA2008 is a power (high current) amplifier that operates at relatively high switching frequencies. The outputs of the amplifier switch between the supply voltage and ground, at high speeds, while driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive LC output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and below ground by the energy in the output inductance. To avoid subjecting the TAA2008 to potentially damaging voltage stress, it is critical to have a good printed circuit board layout. It is recommended that Tripath's layout and application circuit be used for all applications and only be deviated from after careful analysis of the effects of any changes. Please contact Tripath Technology for further information regarding reference design material regarding the TAA2008.
Output Stage layout Considerations and Component Selection Criteria
Proper PCB layout and component selection is a major step in designing a reliable TAA2008 power amplifier. The supply pins require proper decoupling with correctly chosen components to achieve optimal performance and reliability. The output pins need proper protection to keep the outputs from going below ground and above VDD.
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The above layout shows ideal component placement and routing for supply decoupling. C2 and C3 are .1uF surface mount capacitors placed directly across their respective VDD and PGND pins. C1 is a low ESR bulk capacitance electrolytic (at least 100uF). C1's VDD pin is routed to the TAA2008's VDD1 and VDD2 pins on the opposite side of the PCB as the TAA2008. Vias return the supply trace to the TAA2008 side of the PCB at the VDD1 and VDD2 pins. This arrangement allows C1's PGND pin to have a low impedance return path to PGND1 and PGND2 through the PCB's ground plane and allows the output traces (OUTM1, OUTP1, OUTM2, AND OUTP2) to be routed directly to the low pass filter. By having C1's supply pins directly across the TAA2008's VDD and PGND pins supply overshoots will be controlled and mean supply elevation will be reduced. Effectively decoupling VDD will shunt any power supply trace length inductance. The construction of the bulk electrolytic is critical. This capacitor should be a low ESR, ripple rated SMT, or through-hole component. Water based through-hole electrolytic capacitors offer very cost competitive solutions with extremely low impedance (ESR). These include Nichicon HE series and Panasonic FM series. Qualified SMT electrolytics include Nichicon UD series and Panasonic FK series. Panasonic FC capacitors also work well but are likely more costly with no improvement in performance over the capacitor families mentioned above. The output L1 - L4 should be placed close to the TAA2008 without compromising the locations of the closely placed supply decoupling capacitors. The purpose of placing the inductors close to the TAA2008 output pins in to reduce the trace length of the switching outputs. This will aid in reducing radiated emissions. For VDD voltages above 13.2V, or on designs where a tight layout cannot be adhered to due to physical constraints, it is strongly recommended that the value of CSW is increased to 220uF and that both low and high side schottky diodes are implemented. These changes will ensure that the output over shoots will not exceed the absolute maximum rating of 16V. The output diodes, DO, should be located as close to the output pins as possible and returned to their respective PGND or VDD, as shown in the Application / Test Diagram. Please see the External Component Description section on page 6 for more details on the abovementioned components. The Application/ Test Circuit refers to both supply decoupling capacitors as CSW, and the output diodes as DO.
TAA2008 Amplifier Gain
The ideal gain of the TAA2008 is set by the ratio of two external resistors, RI and RF, and is given by the following formula:
VO R = - 12 F VI RI
where VI is the input signal level and VO is the differential output signal level across the speaker. Please note that VO is 180 out of phase with VI.
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The ideal gain of the TAA2008 is 12V/V, whereas typical values are: AV = 11.7V/V for 8. The low frequency roll-off characteristic is dictated by the choice of CI and RI. The -3dB frequency is:
f
- 3dB
=
1 2 C I R I
The figure below shows the roll-off characteristic for different values of CI, assuming an RI value of 20k. As can be seen, the larger the value of CI, the lower the -3dB cutoff point. On the EBTAA2008, a value of 2.2F is used for CI which creates a nearly flat response down to 20Hz. In many cases, a lower value of CI can be used because the speakers used in LCD TV's or similar applications do not have the ability to reproduce low frequency signals.
Frequency Response
+1
+0
-1
C I = 2.2uF
d B r -2
C I = 1.0uF C I = 0.47uF C I = 0.22uF
-3
-4
-5
VD D = 12V P O = 1W R L = 8
20 50 100 200 500 Hz 1k 2k 5k 10k 20k
-6
Mute Pin
The mute pin must be driven to a logic low or logic high state for proper operation. To enable the amplifier, connect the mute pin to a logic low. To enable the mute function, connect the mute pin to a logic high signal. Please note that the mute pin is a 5V CMOS input pin and the mute signal should be de-bounced to eliminate a possibility of falsely muting. When in mute, the internal processor bias voltages are still active in the TAA2008. This minimizes any turn on pop caused by charging the input coupling capacitor. It is recommended that the mute is held high during power up or power down to eliminate audible transients. If turn-on and/or turn-off noise is still present with a TAA2008 amplifier, the cause may be other circuitry external to the TAA2008 such as an audio processor or preamp. Multiple audio processors used in LCD TV's create audible pops as their power supply collapses. If the TAA2008 is still active (mute pin is low), then these audible pops will be amplified and output to the speakers. To eliminate this problem, simply activate the mute before the power supply collapses. The delay going into mute is approximately 1us, as compared to several hundred milliseconds on the previous Tripath IC's such as TA2024B.
Sleep Pin
The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent current mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the pin to be pulled up through a large valued resistor (1M recommended) to VDD. To disable SLEEP mode, the sleep pin should be grounded.
Protection Circuits
The TAA2008 is guarded against over-temperature and over-current conditions. When the device goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH state indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRI11 TAA2008 -KLi/1.0/05.06
Tri path Technol og y, I nc. - Techni cal I nformation
STATED, and will float to 1/2 of VDD. The FAULT pin can be connected directly to MUTE to automatically recover from an overcurrent condition.
Over-temperature Protection
An over-temperature fault occurs if the junction temperature of the part exceeds approximately 155C. The thermal hysteresis of the part is approximately 45C, therefore the fault will automatically clear when the junction temperature drops below 110C.
Over-current Protection
An over-current fault occurs if more than approximately 7 amps of current flows from any of the amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the speaker is shorted to ground. An over-current fault sets an internal latch that can only be cleared if the MUTE pin is toggled or if the part is powered down. Alternately, if the MUTE pin is connected to the FAULT pin, the HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset the fault condition.
Overload
The OVRLDB pin is a 5V logic output. When low, it indicates that the level of the input signal has overloaded the amplifier resulting in increased distortion at the output. The OVRLDB signal can be used to control a distortion indicator light or LED through a simple buffer circuit, as the OVRLDB cannot drive an LED directly.
Fault Pin
The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over current at any output, and junction temperature greater than approximately 155C. All faults except overcurrent automatically reset upon removal of the condition. The FAULT output is capable of directly driving an LED through a series 2k resistor. If the FAULT pin is connected directly to the MUTE input an automatic reset will occur in the event of an over-current condition.
Output Voltage Offset
The DC offset voltages that appear at the speaker terminals of a TAA2008 amplifier are typically small and for most applications no DC offset correction is necessary. The TAA2008 is 100% tested to ensure that the differential output DC offset voltage is less than +/-150mV. However this DC offset can cause a small turn on and turn off pop, depending on the offset value for that specific IC. Every TAA2008 IC will have a different offset voltage for each channel. If the output offset is deemed unacceptable from a turn on/off pop standpoint, there are three recommended methods for correcting it. These methods of trimming the offset voltage are optional and for most cases the additional circuitry is not needed. 1) A potentiometer can be used at the input of the TAA2008 as shown in the figure below. By changing the input bias voltage the output DC offset voltage can be trimmed. Two separate potentiometers must be used to trim both channels.
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OAOUT1 29
CI 2.2uF +
RF RI 20K 20K
INV1 30
ROFB 1M V5A (pin 28) ROFA 10K Offset Trim Potentiometer
TAA2008
COF 0.1uF
OAOUT2
1
CI 2.2uF +
RI 20K
RF 20K
INV2
2
ROFB 1M V5A (pin 28) ROFA 10K Offset Trim Potentiometer
COF 0.1uF
2) In cases where manually trimming potentiometers is not possible, resistors can be used in place of potentiometers. Since each TAA2008 has different offset voltage, the output offset voltage will need to be measured for both channel 1 and channel 2 and then resistors will have to be added on the PC board to trim the offset. Below is a lookup table for resistor values for corresponding offset voltages. Both Rx and Ry values should be 1% tolerance resistors. Please refer to the EB-TAA2008 document for more information on this manual trim method using resistors.
OAOUT1 29
CI 2.2uF +
RI 20K
RF 20K
INV1 30
ROFB 1M V5A (pin 28) RX1 RY1
TAA2008
OAOUT2
1
CI 2.2uF +
RI 20K
RF 20K
INV2
2
V5A (pin 28) RX2 RY2
ROFB 1M
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TAA2008 -KLi/1.0/05.06
Tri path Technol og y, I nc. - Techni cal I nformation
OFFSET 150mV 140mV 130mV 120mV 110mV 100mV 90mV 80mV 70mV 60mV 50mV 40mV 30mV 20mV 10mV 0mV -10mV -20mV -30mV -40mV -50mV -60mV -70mV -80mV -90mV -100mV -110mV -120mV -130mV -140mV -150mV
Ry 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k
Rx (1%) 13.3k 13.7k 14.3k 14.7k 15.4k 15.8k 16.2k 16.9k 17.4k 17.8k 18.7k 19.1k 19.6k 20.5k 21k 21.5k 22.6k 23.2k 24.3k 24.9k 25.5k 26.7k 27.4k 28.0k 29.4k 30.1k 31.6k 32.4k 33.2k 34.8k 35.7k
3) A DC servo using a dual op amp can also be used to automatically null any offset voltage. This DC servo will only eliminate the turn off pop since the RC time constant of the DC servo is very slow. Please contact Tripath sales for additional information on the DC servo circuit.
Power Dissipation Derating
The TAA2008, as a result of high efficiency and good package thermal characteristics, can operate at elevated ambient temperatures without having to derate the output power, assuming 8 ohm output loads or higher. This in stark contrast to many other "competitive" solutions from other semiconductor vendors, many of which can only provide full power at ambient temperatures of 25C, or slightly higher, without exceeding a junction temperature of 150C. Lower die temperatures result in a more robust and reliable amplifier solution that can only be facilitated by a combination of high efficiency and good package thermal characteristics. The exposed pad must be soldered to the PC Board to increase the maximum power dissipation capability of the TAA2008 package. Soldering will minimize the likelihood of an overtemperature fault occurring during continuous heavy load conditions. There should be vias for connecting the exposed pad to the copper area on the printed circuit board.
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Tri path Technol og y, I nc. - Techni cal I nformation
Conducting initial testing or characterization without the exposed pad soldered to the printed circuit board will give erroneous case temperature measurements. The TAA2008 is an extremely robust device, so not soldering the device to the printed circuit board, due to potential rework issues, should not be a concern. These devices do not fail unless the operating supply voltages maximums are exceeded, and/or an improper printed board design is utilized. The maximum device power dissipation, for a given ambient temperature, can be calculated based on a 150C maximum junction temperature, TJMAX, as given by the following equation:
PDISS = (TJMAX - TA ) JA
where: PDISS = maximum power dissipation TJMAX = maximum junction temperature of TAA2008 TA = operating ambient temperature JA = junction-to-ambient thermal resistance = 22C/W when soldered to PCB From the above formula, the maximum power dissipation at an ambient temperature of 25C is 5.68W, and at 70C is 3.64W. The amount of power dissipation can easily be calculated given the output power and efficiency for that output level. The Typical Performance Characteristics section has a significant amount of efficiency and power dissipation data. The relation between PDISS, Output Power and Efficiency is given in the formula below.
PDISS =
Total Output Power - Total Output Power Efficiency
The efficiency for the TAA2008 is 86% at 9 watts per channel. Thus, the power dissipation is:
PDISS =
18W - 18W = 2.93 Watts 0.86
Since 2.93 Watts is less than the maximum power dissipation of 3.64 Watts at 70C, the TAA2008 is not thermally limited assuming maximum output power into 8 ohms loads. The resultant junction temperature, TJ, can be calculated using the formula below:
T J = P DISS * JA + T A
The power dissipation at 9 watts per channel into 8 ohms is 2.93W, as calculated above. Assuming an ambient temperature of 40C, this results in a junction temperature of 105C. This junction temperature is much lower than "competitive" solutions at similar output power levels with 8 ohm loads, resulting in a more reliable amplifier design. A similar set of calculations can be done for a 16 ohm load. But since the efficiency is higher and the output power is lower for a 16 ohm load, as opposed to an 8 ohm load, the power dissipation will be smaller. Since the TAA2008 is not thermally limited into 8 ohm loads, it will not be thermal limited into 16 ohm loads.
Performance Measurements of the TAA2008
The TAA2008 operates by generating a high frequency switching signal based on the audio input. This signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an
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Tri path Technol og y, I nc. - Techni cal I nformation
amplified version of the audio input. The frequency of the switching pattern is spread spectrum and typically varies between 100kHz and 1.0MHz, which is well above the 20Hz - 20kHz audio band. The pattern itself does not alter or distort the audio input signal but it does introduce some inaudible components. The measurements of certain performance parameters, particularly noise related specifications such as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible noise components introduced by the Tripath amplifiers switching pattern will degrade the measurement. One feature of the TAA2008 is that it does not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements. Though using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when they are made with wide-bandwidth measuring equipment), these same filters degrade frequency response. The TAA2008 Evaluation Board uses the Test/Application Circuit in this data sheet, which has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument.
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Tri path Technol og y, I nc. - Techni cal I nformation
PACKAGE INFORMATION
32 PIN QFN - 8MM x 8MM X 1MM
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TAA2008 -KLi/1.0/05.06
Tri path Technol og y, I nc. - Techni cal I nformation
Tripath Technology Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. Tripath and Digital Power Processing are trademarks of Tripath Technology Inc. Other trademarks referenced in this document are owned by their respective companies. TRIPATH'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Contact Information
TRIPATH TECHNOLOGY, INC 2560 Orchard Parkway, San Jose, CA 95131 408.750.3000 - P 408.750.3001 - F For more Sales Information, please visit us @ www.tripath.com/cont_s.htm For more Technical Information, please visit us @ www.tripath.com/data.htm
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TAA2008 -KLi/1.0/05.06

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